Method and system for detecting a mode of operation of an integrated circuit, and a memory device including same

ABSTRACT

A threshold detection circuit for developing a mode trigger signal includes an input that receives an input signal. In response to the input signal having approximately an input threshold value for a triggering time, the threshold detection circuit activates the mode trigger signal on an output. In response to the input signal being substantially different from the input threshold value or the input signal not having the input threshold value for the triggering time, the circuit deactivates the mode trigger signal. The threshold detection circuit may be contained in a variety of different mode detection circuits for detecting when an integrated circuit is to be placed in a test mode or other desired mode of operation, and such mode detection circuits may be contained in a variety of different types of integrated circuits, such as memory devices generally and SRAMs specifically.

TECHNICAL FIELD

The present invention relates generally to semiconductor integratedcircuits, and more specifically to detecting conditions associated withthe operation of semiconductor integrated circuits such as memorydevices.

BACKGROUND OF THE INVENTION

In semiconductor memory devices and other semiconductor integratedcircuits, the devices are typically placed in a test mode of operationduring manufacture to ensure that the devices operate as required. Avariety of different techniques are utilized to place the device in thea particular mode of operation, such as a test mode of operation. Forexample, in a dynamic random access memory (“DRAM”), a particularsequence of applied control signals may be applied to place the devicein the test mode of operation, such as activating a column addressstrobe signal CAS before a row address signal RAS, which does not occurduring normal operation of the memory device. Another conventionalmethod for placing a memory device in a test mode of operation is toapply a “supervoltage” to a particular pin of the memory device. Thesupervoltage has a value greater than the normal operating range ofsignals applied on the pin, and when circuitry within the memory devicesenses the supervoltage, the device begins operating in the test mode.

In some situations, however, a particular technology limits theutilization of the supervoltage approach to placing the memory device inthe test mode. For example, in a static random access memory (“SRAM”),at least some external pins of the memory typically include diodescoupled between the pin and a supply voltage to provide clamping ofsignals applied to the pin. FIG. 1 is a functional diagram illustratingan external pin 100 of an SRAM coupled to internal circuitry 102 in theSRAM. A clamping diode 104 is coupled between the external pin and asupply voltage VCC to limit or “clamp” voltages on the external pin 100and thereby prevent such voltages from damaging the internal circuitry102. When such diodes 104 are utilized, it is not possible to apply asupervoltage to the external pin 100 to place the SRAM in a test mode ofoperation since the clamping diode 104 limits the voltage on theexternal pin to a threshold voltage VT of the diode above the supplyvoltage VCC. This is true because the clamping diode 104 prevents thevoltage on the pin from being driven to a level sufficiently abovenormal operating levels to allow the internal circuitry 102 to reliablydetect the presence of the supervoltage and place the SRAM in the testmode of operation. Moreover, a permissible range of values for thesupply voltage VCC may include the value VCC+VT and thus this voltagecannot not be used to place the SRAM in the test mode.

With any technique for placing an integrated circuit in a test mode ofoperation, it must be extremely unlikely that the test mode can beinadvertently entered by a user of the memory device. It must beextremely unlikely that the test mode will be inadvertently enteredbecause entering the test mode will typically render the deviceinoperable. For example, in a typical memory device, during the testmode redundant circuits are utilized to replace defective elements inthe device. If the test mode of the device is reentered, such redundantelements are typically disabled to allow for testing of the device.Thus, if a customer were to inadvertently enter the test mode, thedevice would become inoperable since the redundant elements beingutilized to replace defective elements in the memory device will bedisabled.

There is a need for a reliable technique to place a wide variety ofintegrated circuits into a test or other desired mode of operation wherethe use of one or more of the existing approaches is not viable.

SUMMARY OF THE INVENTION

According to one aspect of the present invention, a method of detectinga mode of operation of an integrated circuit includes receiving a signalhaving a first level corresponding to a first logic state and a secondlevel corresponding to a second logic state. The signal has a midpointbeing defined between the first and second logic states. The methoddetects whether the signal is approximately at the midpoint and when thesignal is detected at the midpoint, the mode of operation is detected.The detected mode of operation may be a test or other mode of operationof the integrated circuit.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a simplified functional diagram of an external pin in aconventional SRAM.

FIG. 2A is a functional block diagram of midpoint detection circuit andoutput circuit according to one embodiment of the present invention.

FIG. 2B is a signal diagram illustrating a sample of the input signalapplied to the midpoint detection circuit of FIG. 2A.

FIG. 3 is a functional block diagram of another embodiment of themidpoint detection circuit 200 of FIG. 2A.

FIG. 4 is a schematic of a threshold detection circuit according to oneembodiment of the present invention.

FIG. 5 is a functional block diagram illustrating one embodiment of atest mode detection circuit including a number of the thresholddetection circuits of FIG. 4.

FIG. 6 is a functional block diagram illustrating another embodiment ofa test node detection circuit including the threshold detection circuitof FIG. 4.

FIG. 7 is a functional block diagram of a memory device including thetest mode detection circuit of FIGS. 5 or 6 and/or the thresholddetection circuit of FIGS. 2 and 3 according to one embodiment of thepresent invention.

FIG. 8 is a functional block diagram of a computer system including thememory device of FIG. 7.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 2A is a functional block diagram of a midpoint detection circuit200 that detects a midpoint MP of an input signal SIN and generates amidpoint signal MS indicating whether the midpoint level has beendetected, with the MS signal being utilized to indicate a variety ofdifferent conditions such as a specific mode of operation to be enteredby an output circuit 202 receiving the MS signal, as will be describedin more detail below. A myriad of different types of circuits canreceive the MS signal and perform some operation in response to thatsignal, and in FIG. 2A these circuits are illustrated generically as theoutput circuit 202 that generates an output signal SOUT responsive tothe MS signal.

In the following description, certain details are set forth to provide asufficient understanding of the present invention, but one skilled inthe art will appreciate that the invention may be practiced withoutthese particular details. Furthermore, one skilled in the art willappreciate that the example embodiments described below do not limit thescope of the present invention, and will also understand that variousmodifications, equivalents, and combinations of the disclosed exampleembodiments and components of such embodiments are within the scope ofthe present invention. The operation of well known components has notbeen shown or described in detail in the following description to avoidunnecessarily obscuring the present invention.

The SIN signal may be any type of signal having a high voltage VHcorresponding to a first logic state and a low voltage VL correspondingto a second logic state. The midpoint of the SIN signal detected by thedetection circuit 200 is designated MP in the signal diagram of FIG. 2B,and may lie anywhere between the high voltage VH and low voltage VL.Thus, the midpoint MP need not necessarily lie exactly at the half waypoint between the two voltages (i.e., need not be at (VL+(VH−VL))/2).The significance of the SIN signal being at the midpoint MP may indicateany of a variety of conditions, desirable or undesirable, and the SINsignal may need to remain at the midpoint for a long or short durationdepending on the condition being detected by the midpoint detectioncircuit 200, as will be described in more detail below.

In one embodiment, the midpoint detection circuit 200 is formed by aPMOS transistor 204 and NMOS transistor 206 coupled to form aconventional inverter except that a resistor 208 is coupled between anoutput node 210 corresponding to the drain of the PMOS transistor and anoutput node 212 corresponding to the drain of the NMOS transistor. Themidpoint signal MS corresponds to the voltage across the resistor 208and hence across nodes 210/212 in this embodiment. Each of thetransistors 204, 206 has an associated threshold voltage VT, and themidpoint MP corresponds to a voltage value where the gate-to-sourcevoltage of each transistor is greater than the associated thresholdvoltage so that both transistors are turned ON at the same time. In oneembodiment of the midpoint detection circuit 200 formed by thetransistors 204, 206 and the resistor 208, the circuit operates at 0.5volts and a current ranging from 200 microamps to 10 milliamps, with theresistor having a value ranging from 50 ohms to 2500 ohms.

In operation, when the SIN signal is at the midpoint MP, bothtransistors 204, 206 are turned ON, and current flows from the supplyvoltage source VCC through the series connected PMOS transistor,resistor 208, and NMOS transistor. In response to this current throughthe resistor 208, a voltage develops across the nodes 210, 212 whichcorresponds to the MS signal. Thus, when the SIN signal is at themidpoint MP the MS signal has a non-zero voltage corresponding to thevoltage across nodes 210, 212. In contrast, when the SIN signal is at alevel other than the midpoint MP, one of the transistors 204, 206 isturned OFF, resulting in no current to flow through the resistor 208 andthereby driving the voltage of the MS signal to approximately zero.

Accordingly, when the SIN signal is at the midpoint MP the detectioncircuit 200 outputs a non-zero MS signal and otherwise outputs anapproximately zero MS signal.

In response to the MS signal, the output circuit 202 drives the SOUTsignal to a first value when the MS signal is non-zero and to a secondlevel when the MS signal is approximately zero. The SOUT signal thus hasthe first value when the SIN signal is at the midpoint MP and has thesecond value otherwise. The output circuit 202 can be formed by adifferential amplifier or an operational amplifier that operates inresponse to the MS signal to generate the SOUT signal, and suitablecircuitry for forming each of these amplifiers will be understood bythose skilled in the art.

FIG. 3 is a functional block diagram of another embodiment of themidpoint detection circuit 200 of FIG. 2A. In this embodiment, themidpoint detection circuit 200 is formed by a pair of differentialamplifiers 222, 224, each receiving a respective reference voltageVREF1, VREF2 on one input and having a second input receiving the SINsignal. In this embodiment, output signals from the differentialamplifiers 222, 224 correspond to the MS signal, and the output circuit202 (FIG. 2A) is formed by logic circuitry that develops the SOUT signalresponsive to the MS signal. In operation, when the SIN signal is at themidpoint MP, which is within a range of values between two logic states,each differential amplifier 222, 224 drives its corresponding outputsignal to an activation level. When the output circuit 202 (FIG. 2A)receives output signals from both differential amplifiers 222, 224having the activation level, the output circuit activates the SOUTsignal. When the SIN signal has a value other than the midpoint MP, onlyone of the output signals from the differential amplifiers 222, 224 butnot both are at the corresponding activation level, and in thissituation the logic circuitry deactivates the SOUT signal.

As previously mentioned, the significance of the SIN signal being at themidpoint MP and thus the generation of the MS signal may indicate any ofa variety of conditions. For example, the midpoint detection circuit 200may be contained in a memory device such as a DRAM and the generation ofthe MS signal upon detection of SIN signal at the midpoint MP utilizedto change the width of a data bus DQ of the DRAM, such as from a widthof 16 bits to a width of 8 bits. Another example is the entry of aparticular configuration mode of a DRAM upon detection of the SIN at themidpoint MP, such as the mode of a conventional DRAM in which data isstored in a load mode register to set such operating parameters as burstlength and type for the DRAM. Alternatively, the detection of the SINsignal at the midpoint MP for a certain time my indicate a problem withthe DRAM or other device, and the corresponding MS signal may correspondto a warning or repair signal upon which action may be taken toeliminate the problem. In still another example, the midpoint detectioncircuit 200 can operate as an address transition detector, such as iscontained in an asynchronous SRAM to detect the transition of addresssignals applied to the SRAM so that other operations in the SRAM canperformed relative to the detection of such address transitions. In allthese examples, the SIN signal corresponds to some signal applied to thememory or other device, such as an address signal in the addresstransition detector example. These examples are not intended to be anexhaustive list of applications for or embodiments of the presentinvention, and various modifications, equivalents, and combinations ofthe disclosed example embodiments and components thereof are within thescope of the present invention.

FIG. 4 is a schematic illustrating another embodiment of a thresholddetection circuit 250 that detects when an applied input voltage signalVIN is maintained at a voltage threshold value for a required triggertime and activates a test mode latch signal TMLA when this is true, aswill be explained in more detail below. The threshold detection circuit250 is typically contained in a memory device or other integratedcircuit, and is used to detect the input voltage signal VIN applied onan external terminal 502 of the device and to activate the TMLA signalwhen the signal VIN has the required characteristics to place the devicein a test or other desired mode of operation. The threshold detectioncircuit 250 includes a PMOS transistor 504 and an NMOS transistor 506coupled as in a conventional inverter circuit, except that a thresholdresistor 509 is coupled between the respective drains of thetransistors. In operation, the transistors 504, 506 operate in one oftwo modes, a normal mode and a test mode. In the normal mode, thetransistors 504, 506 operate as they do in a conventional inverter inresponse to the applied input voltage signal VIN being at first andsecond voltage levels corresponding to first and second binary logicstates. Thus, when the applied input voltage signal VIN is low, thetransistor 506 turns OFF and the transistor 504 turns ON, driving anoutput voltage VOUT high. When the applied input voltage signal VIN ishigh, the transistor 506 turns ON and the transistor 504 turns OFF,driving the output voltage VOUT low. In the test mode, the input voltagesignal VIN is maintained at a voltage threshold value, causing thetransistors 504, 506 to simultaneously turn ON and causing current toflow through the threshold resistor 508 to thereby develop a testvoltage VTST across the threshold resistor.

The term “voltage threshold value” is used relative to a device, such asan inverter, and corresponds to a voltage value or “trip point” that anapplied input to the device must cross in order to initiate a change inthe logic state of an output of the device. During normal operation ofsuch a device, an applied input is not maintained at the voltagethreshold value for any particular time, but instead the input merelypasses through the threshold voltage as it transitions from one logicstate to another. In other words, during the normal mode of operation,the input voltage signal VIN passes through the voltage threshold valuewhen transitioning between logic states, and is thus only at the voltagethreshold value for a very short time so that substantially no currentflows through the resistor 508. In contrast, during the test mode, theinput voltage signal VIN is maintained at approximately the voltagethreshold value so that the test voltage VTST develops across theresistor 508.

The threshold detection circuit 250 further includes a PMOS transistor510 having its gate and source coupled across the resistor 508 andhaving its drain coupled to a charging node 512. A capacitor 514 andresistor 516 are coupled between the charging node 512 and ground, andwhen the transistor 510 turns ON in response to the test voltage VTSTthe capacitor begins charging. As the capacitor 514 is charging, atrigger voltage VTRIG on the node 512 begins increasing, with the rateat which the trigger voltage increases being a function of the values ofthe capacitor 514 and the resistor 516 as well as value of the testvoltage VTST and the size of the transistor 510, as will be appreciatedby those skilled in the art. An NMOS transistor 518 receives a clocksignal CLK, and when the clock signal is active high the transistorturns ON to discharge the capacitor 514 and drive the trigger voltageVTRIG to approximately ground. A comparator 520 develops the test modelatch signal TMLA in response to the trigger voltage VTRIG, driving theTMLA signal active high when the trigger voltage is greater than atrigger value of the comparator, and driving the TMLA signal inactivelow when the voltage is less than the trigger value.

In operation, the threshold detection circuit 250 operates in two modes,a normal mode and a test mode, which correspond to normal and test modepreviously described with reference to the transistors 504, 506. In thenormal mode, the input voltage signal VIN is either high or low, causingthe transistors 504, 506 to alternately turn ON as previously describedand drive the output voltage VOUT either low or high. When thetransistors 504 and 506 are alternately activated, substantially nocurrent flows through the resistor 508 so that the test voltage VTST issubstantially zero. When the test voltage VTST is substantially zero,the transistor 510 is turned OFF because the gate-to-source voltageapplied to the transistor is approximately zero, and the capacitor 514is not charged. During the normal mode, the CLK signal toggles andperiodically turns ON the transistor 518 when the CLK signal high, withthe frequency of the CLK signal being sufficient to thereby drive thetrigger voltage VTRIG low. In response to the low trigger voltage VTRIG,the comparator 520 drives the TMLA signal inactive low. Thus, in thenormal mode the threshold detection circuit 250 operates as aconventional inverter and the TMLA signal is driven in active low.

During the test mode of operation, the input voltage signal VIN ismaintained at the voltage threshold value, causing the transistors 504,506 to both simultaneously turn ON and causing current to flow throughthe threshold resistor 508 to thereby develop the test voltage VTSTacross the threshold resistor. The CLK signal is driven inactive lowduring the test mode, turning OFF the transistor 518. In response to thetest voltage VTST, the transistor 510 turns ON and the capacitor 514begins charging. When the trigger voltage VTRIG reaches the triggervalue of the comparator 520, the comparator drives the TMLA signalactive high. Note that the test voltage VTST is developed across thethreshold resistor 508 only as long as the input voltage signal VIN ismaintained at approximately the voltage threshold value. Thus, the inputvoltage signal VIN must be maintained at approximately the voltagethreshold value for a minimum time so that the test voltage VTST acrossthe resistor 508 turns ON the transistor 510 to charge the capacitor 514until the trigger voltage VTRIG exceeds the trigger value of thecomparator 520. If the input voltage signal VIN deviates fromapproximately the voltage threshold value before this minimum time, thetest voltage VTST will go to approximately zero as previously described,turning OFF the transistor 510 which, in turn, stops the charging of thecapacitor 514. At this point, the trigger voltage VTRIG is less than thetrigger value of the comparator 520 so the TMLA signal is maintainedinactive low. It should also be noted that at this point the capacitor514 begins discharging through the resistor 516.

The threshold detection circuit 250 may be formed in a variety ofdifferent types of integrated circuits, and utilized to detect a testmode of the integrated circuit via the test mode of the thresholddetection circuit. Thus, when the integrated circuit containing thethreshold detection circuit 250 is to be placed in a test mode ofoperation, the input voltage signal VIN is held at the voltage thresholdvalue for a sufficient time to activate the TMLA signal and therebyplace the integrated circuit in the test mode of operation. Thethreshold detection circuit 250 thus provides a reliable way to place anintegrated circuit in a test mode of operation since it is very unlikelythat during normal operation of the integrated circuit, the inputvoltage signal VIN would ever be maintained at the voltage thresholdvalue for the minimum time required to activate the TMLA signal. Inaddition, note that the threshold detection circuit 250 eliminates theneed for the use of a supervoltage to place the integrated circuit inthe test mode. Moreover, unlike a supervoltage the voltage thresholdvalue has a value between the high and low voltage levels of the inputvoltage signal VIN and thus presents no concerns regarding clamping ofthe applied voltage by clamping diodes (see FIG. 1) coupled to pins ofthe integrated circuit. The threshold detection circuit 250 could alsobe utilized as a conventional inverter during the normal mode ofoperation although typically a conventional inverter would be coupled inparallel with the threshold detection circuit for use during the normalmode.

In the threshold detection circuit 250, the speed of operation of thecircuit can be increased by removing either the capacitor 514 orresistor 516, which may be useful in some applications of the circuitsuch as an address detection circuit where the VIN signal is only at thevoltage threshold value or midpoint for a short time. Removal of thecapacitor 514 allows the voltage VTRIG to develop across the resistor516 as soon as transistor 510 turns ON. When the resistor 516 isremoved, the voltage VTRIG across the capacitor 514 increases morequickly once the transistor 510 is turned ON. In both situations, thevoltage VTRIG exceeds the trigger value of the comparator 520 morequickly, causing the comparator to drive the TMLA signal active morequickly in response to the VIN signal being at the midpoint.

FIG. 5 is a functional block diagram illustrating one embodiment of atest mode detection circuit 300 including three threshold detectioncircuits 302-306, each of the threshold detection circuits beingidentical to the threshold detection circuit 250 of FIG. 4. Althoughthree threshold detection circuits 302-306 are illustrated in theembodiment of FIG. 5, fewer or more threshold detection circuits may beincluded in alternative embodiments. Each of the threshold detectioncircuits 302-306 receives a corresponding input voltage signal VIN1-VIN3applied to a corresponding pin of an integrated circuit containing thetest mode detection circuit 300. Each threshold detection circuit302-306 generates a corresponding test mode latch signal TMLA1-TMLA3 inthe same manner as previously described with reference to the detectioncircuit 250 of FIG. 4. In the test mode detection circuit 300, a modeevaluation circuit 308 receives the test mode latch signals TMLA1-TMLA3and activates a test mode indication signal TMI when all of the testmode latch signals are active. In this embodiment, the test modeindication signal TMI is the signal that places the integrated circuitcontaining the test mode detection circuit 300 into the test mode ofoperation.

The test mode detection circuit 300 allows multiple threshold detectioncircuits 302-306 to be utilized to place the integrated circuit into thetest mode and thereby provides added protection against inadvertentlyentering the test mode. This is true because in order for the modeevaluation circuit 308 to activate the TMI signal, instead of a singleinput voltage signal, the three input voltage signals VIN1-VIN3 must bemaintained at the corresponding voltage threshold values for thecorresponding required times in order for the threshold detectioncircuits 302-306 to activate the TMLA1-TMLA3 signals. It is extremelyunlikely that all of the input voltage signals VIN1-VIN3 would bemaintained at the corresponding voltage threshold values for therequired times. In FIG. 5, each of the threshold detection circuits302-306 is shown as having an associated voltage threshold value VT1-VT3and an associated time constant T1-T3. The voltage threshold valuesVT1-VT3 correspond to the voltage threshold values at which each of theinput voltage signals VIN1-VIN3 must be maintained in order for thethreshold detection circuits 302-306 to activate the TMLA1-TMLA3signals, respectively. Thus, each of the circuits 302-306 may have adifferent voltage threshold value VT1-VT3 to provide added protectionagainst inadvertent entry into the test mode. Each of the time constantsT1-T3 corresponds to the time the corresponding input voltage signalVIN1-VIN3 must be maintained at the corresponding voltage thresholdvalue VT1-VT3. In other words, each of the time constants T1-T3corresponds to the time the signal VIN1-VIN3 must be maintained at thethreshold value VT1-VT3 in order for the capacitor 514 (FIG. 4) tocharge to the trigger voltage VTRIG. In the test mode detection circuit300, the voltage threshold values VT1-VT3 may all be different or mayall be the same, and the same is true of the time constants T1-T3.

Several alternative embodiments of the test mode detection circuit 300are also illustrated in FIG. 5. In one alternative embodiment, the TMIsignal is applied to a test mode register 310 that receives a pluralityof test mode signals TM1-TMN on respective external terminals of theintegrated circuit containing the test mode detection circuit 300. Thetest mode register 310 latches the TM1-TMN signals responsive to the TMIsignal. The test mode register 310 also receives a test mode enablesignal TME that is applied to an external terminal of the integratedcircuit, and the register provides the latched TM1-TMN signals on anoutput 312 responsive to the TME signal going active. Each of the testmode signals TM1-TMN defines a particular test or mode to be executedduring the test mode operation of the integrated circuit. For example,one test mode signal TM1-TMN may define the specific test, data patternto be written to memory cells contained within the integrated circuit,or may define a specific voltage stress test to be performed upon suchmemory cells. In this embodiment, when the TMI signals goes active thetest mode register 310 latches the test mode signals TM1-TMN and whenTME signal goes active the register 310 provides the latched test modesignals TM1-TMN on the output 312 to thereby invoke the test mode ofoperation.

In another alternative embodiment, the test mode detection circuit 300includes only two threshold detection circuits 302 and 304, each of thethreshold detection circuits coupled to a respective pin of a devicecontaining the threshold detection circuit to receive a respectivecomplementary logic signal. For example, the threshold detectioncircuits 302, 304 could receive complementary clock signals CLK and CLK,respectively. The circuits 302, 304 thereafter operate in combinationwith the mode evaluation circuit 308 as previously described to generatethe TMI signal to place the integrated circuit in the test mode. In thisembodiment, the use of the threshold detection circuits 302, 304 on pinsthat receive complementary signals provides added protection againstinadvertent entry into the test mode since it is extremely unlikely boththe complementary signals would be maintained at the required inputthreshold values for the required times. In any of these alternativeembodiments, the voltage threshold values VT1-VT3 and time constantsT1-T3 of the threshold detection circuits 302-306 may be the same ordifferent, as will be appreciated by those skilled in the art.

In the test mode detection circuit 300 of FIG. 5, the mode evaluationcircuit 308 may be formed from a simple AND gate in some embodiments andfrom a state machine in other embodiments. For example, in oneembodiment the circuit 300 includes a single threshold detection circuit302, and in this embodiment the mode evaluation circuit 308 is a statemachine that monitors the signal VIN1 applied on a corresponding pin todetect the test mode of operation. In this embodiment, the signal VIN1is sequentially activated for different time constants, and the modeevaluation circuit 308 detects a required sequence of time constants forthe signal VIN1 and activates the TMI signal when this sequence isdetected. In embodiments where multiple threshold detection circuits 302are utilized, the time constants of the corresponding signals VINapplied to the threshold detection circuits may be the same for eachsignal or may vary among signals. Similarly, the voltages of the signalsVIN may each be the same or may vary among signals VIN in such multiplethreshold detection circuit 302 embodiments. In other embodimentsincluding multiple threshold detection circuits 302, both voltages andtime constants may vary among signals VIN. The mode evaluation circuit308 may be formed by a state machine in such multiple thresholddetection circuit 302 embodiments. Where multiple threshold detectioncircuits 302 are utilized and the time constants of each are the same,the mode evaluation circuit 308 may be formed from an AND gate.

FIG. 6 illustrates a test mode detection circuit 400 according to yetanother embodiment of the present invention. The test mode detectioncircuit 400 includes a threshold detection circuit 402, which isidentical to the threshold detection circuit 250 previously describedwith reference to FIG. 4. The threshold detection circuit 402 receives apulse input signal PI that is a periodic signal maintained at thevoltage threshold value of the detection circuit for a portion of theperiod of the signal and is maintained at a low logic level during theremainder of the period. The portion of the period for which the pulseinput signal PI is maintained at the voltage threshold value issufficient to cause the threshold detection circuit 402 to activate itsoutput, which is indicated as a test clock signal TCLK in FIG. 6. TheTCLK signal corresponds to the TMLA signal of the threshold detectioncircuit 250 previously described with reference to FIG. 4, but isdesignated as a clock signal to indicate that the signal is periodic inresponse to the periodic pulse input signal PI. The TCLK signal clocks acounter 404 that increments a count in response to being clocked, andactivates the TMLA signal when the count reaches a desired value. Thecounter 404 may also receive additional signals 406 applied on externalterminals of the integrated circuit containing the test mode detectioncircuit 400. When the counter 404 receives the additional signals 406,the counter 404 activates the TMLA signal when the count reaches thedesired value and the signals 406 have predetermined values.

In operation, the counter 404 initially resets the count and the pulseinput signal PI is applied to the threshold detection circuit 402 which,in turn, clocks the TCLK signal. In response to the TCLK signal, thecounter 404 increments the count and when the count reaches the desiredvalue and the additional signals 406 have the predetermined values, thecounter activates the TMLA signal placing the integrated circuitcontaining the test mode detection circuit 400 into the test mode ofoperation. In the test mode detection circuit 400, the required periodicnature of the pulse input signal PI provides protection againstinadvertent entry into the test mode of operation, as will beappreciated by those skilled in the art.

FIG. 7 is a block diagram of a memory device 500 including the test modedetection circuit 300 of FIG. 5. Although the memory device 500 is shownas including the circuit 300, the test mode detection circuit 400 ofFIG. 6 and any of the various embodiments of the test mode detectioncircuits previously described may be contained in the memory device. Inaddition, the memory device 500 may contain the threshold detectioncircuit 200 of FIGS. 2-3 as well for placing the memory device in a testor some other mode of operation as previously discussed. In response tothe IT signals applied to the memory device 500, the test mode detectioncircuit 300 provides the TMLA signal to a test control circuit 502. Thetest control circuit 502 is coupled to a memory-cell array 504 andcontrols test data being transferred to and from memory cells (notshown) in the array during one of many possible test modes of operation.The test control circuit 502 places the memory device 500 in the testmode of operation when the TMLA signal is active and a test mode enablesignal TME applied on an external terminal of the memory device is alsoactive. The TME signal may be omitted in other embodiments of the testcontrol circuit 502. The memory device 500 further includes an addressdecoder 506, a control circuit 508, and read/write circuitry 510, all ofwhich are conventional and known in the art. The address decoder 506,control circuit 508, and read/write circuitry 510 are all coupled to thememory-cell array 504. In addition, the address decoder 506 is coupledto an address bus, the control circuit 508 is coupled to a control bus,and the read/write circuitry 510 is coupled to a data bus.

In operation, external circuitry (not shown) provides address, control,and data signals on the respective busses to the memory device 500.During a read cycle, the external circuitry provides a memory address onthe address bus and control signals on the control bus to the memorydevice 10. In response to the memory address on the address bus, theaddress decoder 506 provides a decoded memory address to the memory-cellarray 504 while the control circuit 508 provides control signals to thememory-cell array 504 in response to the control signals on the controlbus. The control signals from the control circuit 508 control thememory-cell array 504 to provide data to the read/write circuitry 510.The read/write circuitry 510 then provides this data on the data bus foruse by the external circuitry. During a write cycle, the externalcircuitry provides a memory address on the address bus, control signalson the control bus, and data on the data bus. Once again, the addressdecoder 506 decodes the memory address on the address bus and provides adecoded address to the memory-cell array 504. The read/write circuitry510 provides the data on the data bus to the memory-cell array 504 andthis data is stored in the addressed memory cells in the memory-cellarray under control of the control signals from the control circuit 508.During the test mode of operation, the external circuit provides the ITsignals to the circuit 300, which, in turn, activates the TMLA signalwhen the IT signals have the required characteristics. The externalcircuit also activates the TME signal, and when the TME and TMLA signalsare active, the test control circuit .502 test the memory cells in thearray 504. The memory device 500 may be any of a variety of differenttypes of memory device, such as an SRAM, MRAM, DRAM, SDRAM, DDR DRAM,SLDRAM, and RAMBUS DRAM. Moreover, the circuit 300 may be placed inintegrated circuits other than memory devices, such as digital signalprocessors and microprocessors, and the circuit 300 may be used toactivate modes of operation other than a test mode.

FIG. 8 is a block diagram of a computer system 600 which uses the memorydevice 500 of FIG. 7. The computer system 600 includes computercircuitry 602 for performing various computing functions, such asexecuting specific software to perform specific calculations or tasks.In addition, the computer system 600 includes one or more input devices604, such as a keyboard or a mouse, coupled to the computer circuitry602 to allow an operator to interface with the computer system.Typically, the computer system 600 also includes one or more outputdevices 606 coupled to the computer circuitry 602, such output devicestypically being a printer or a video terminal. One or more data storagedevices 608 are also typically coupled to the computer circuitry 602 tostore data or retrieve data from external storage media (not shown).

Examples of typical data storage devices 608 include hard and floppydisks, tape cassettes, and compact disk read only memories (CD-ROMs).The computer circuitry 602 is typically coupled to the memory device 500through a control bus, a data bus, and an address bus to provide forwriting data to and reading data from the memory device.

It is to be understood that even though various embodiments andadvantages of the present invention have been set forth in the foregoingdescription, the above disclosure is illustrative only, and changes maybe made in detail, and yet remain within the broad principles of theinvention. For example, many of the components described above may beimplemented using either digital or analog circuitry, or a combinationof both, and also, where appropriate, may be realized through softwareexecuting on suitable processing circuitry. Therefore, the presentinvention is to be limited only by the appended claims.

1-64. (canceled)
 65. A mode detection circuit, comprising: an inputcircuit having an input and first and second outputs, the input circuitconfigured to generate a voltage differential between first and secondoutputs in response to receiving an input signal having a mode entryvoltage sustained for a mode entry time; and an output circuit coupledto the first and second outputs and having a mode signal output, theoutput circuit configured to generate an active mode signal indicativeof mode entry in response to detecting the voltage differential betweenthe first and second outputs.
 66. The mode detection circuit of claim 65wherein the input circuit comprises: a resistor; a p-channel fieldeffect transistor (PFET) having a gate coupled to the input and a draincoupled to the resistor; and an n-channel field effect transistor (NFET)having a gate coupled to the input and a drain coupled to the resistor,the mode entry voltage equal to a voltage causing both the PFET and NFETto conduct.
 67. The mode detection circuit of claim 66 wherein theoutput circuit comprises: a transistor having a control terminal coupledto the first output of the input circuit and further having a secondterminal coupled to the second output of the input circuit; and anenergy storage element coupled to a third terminal of the transistor,the energy storage element configured to store energy in response to avoltage differential across the first and second outputs of the inputcircuit, the active mode signal having a value that is a function of arate at which the energy storage element stores energy and the durationthat the input signal is approximately at the mode entry voltage. 68.The mode detection circuit of claim 65 wherein the input circuitcomprises: a first differential amplifier having a first input coupledto the input of the input circuit and a second input coupled to a firstreference voltage; and a second differential amplifier having a firstinput coupled to the input of the input circuit and a second inputcoupled to a second reference voltage different than the first referencevoltage.
 69. A mode detection circuit, comprising: a mode-entrydetection circuit having an input and an output, the input adapted toreceive an input signal, the input signal having a first and secondvalues when in a first mode, the mode-entry detection circuit operableto detect the input signal being approximately at a third value for amode-entry time and correspondingly generate on the output a mode-entrysignal indicative of entering a second mode, the third value beingbetween the first and second values.
 70. The mode detection circuit ofclaim 69, wherein the mode-entry detection circuit comprises: a firstcomparison circuit having a first input adapted to receive the inputsignal, a second input coupled to a first reference voltage, and anoutput adapted to generate a first detection signal; a second comparisoncircuit having a first input adapted to receive the input signal, asecond input coupled to a second reference voltage, and an outputadapted to generate a second detection signal; and an output circuitadapted to receive the first and second detection signals, the outputcircuit operable to generate the mode-entry signal responsive to theinput signal being approximately at the third value for the mode-entrytime.
 71. The mode detection circuit of claim 70, wherein at least oneof the first and second comparison circuits comprises a differentialamplifier.
 72. The mode detection circuit of claim 69, wherein themode-entry detection circuit comprises: a load element having a firstand second terminals; a first switching circuit having a controlterminal adapted to receive the input signal, a first signal terminalcoupled to a first reference voltage, and a second signal terminalcoupled to the first terminal of the load element and adapted togenerate a first detection signal; a second switching circuit having acontrol terminal adapted to receive the input signal, a first signalterminal coupled to a second reference voltage, and a second signalterminal coupled to the second terminal of the load element and adaptedto generate a second detection signal; and an output circuit adapted toreceive the first and second detection signals, the output circuitoperable to generate the mode-entry signal responsive to the inputsignal being approximately at the third value for the mode-entry time.73. The mode detection circuit of claim 72, wherein the load elementcomprises a resistor, the first switching circuit comprises a p-channelmetal-oxide-semiconductor (PMOS) transistor, and the second switchingcircuit comprises an n-channel metal-oxide-semiconductor (NMOS)transistor.
 74. The mode detection circuit, of claim 72, wherein theoutput circuit comprises: a third switching circuit having a controlterminal adapted to receive the second detection signal, a first signalterminal adapted to receive the first detection signal, and a secondsignal terminal adapted to develop a charging signal; and an energystorage element adapted to receive the charging signal and store energyfrom the charging signal to develop the mode-entry signal, the developedmode-entry signal having a value as a function of a rate at which theenergy storage element stores energy and a duration of time that theinput signal is approximately at the third value.
 75. The mode detectioncircuit of claim 74, wherein the output circuit further comprises acomparator having an input adapted to receive the mode-entry signal andan output, the comparator operable to generate a mode-latch signal onthe output responsive to the mode-entry signal exceeding a thresholdvalue.
 76. The mode detection circuit of claim 74, wherein the thirdswitching circuit comprises a PMOS transistor, and wherein the energystorage element comprises a capacitor coupled between the second signalterminal of the third switching circuit and the second referencevoltage, a resistor coupled in parallel with the capacitor, and atransistor having a first and second signal terminals coupled inparallel with the capacitor and a control terminal adapted to received aclock signal, the transistor coupling the first and second signalterminals together to discharge the capacitor responsive to the clocksignal.
 77. The mode detection circuit of claim 74, wherein the thirdswitching circuit comprises a PMOS transistor, and wherein the energystorage element comprises a capacitor coupled between the second signalterminal of the third switching circuit and the second referencevoltage, and a transistor having a first and second signal terminalscoupled in parallel with the capacitor and a control terminal adapted toreceived a clock signal, the transistor coupling the first and secondsignal terminals together to discharge the capacitor responsive to theclock signal.
 78. The mode detection circuit of claim 74, wherein thethird switching circuit comprises a PMOS transistor, and wherein theenergy storage element comprises a resistor coupled between the secondsignal terminal of the third switching circuit and the second referencevoltage, and a transistor having a first and second signal terminalscoupled in parallel with the capacitor and a control terminal adapted toreceived a clock signal, the transistor coupling the first and secondsignal terminals together to short-circuit the resistor responsive tothe clock signal.
 79. A mode detection circuit, comprising: an inputcircuit configured to receive an input signal and to generate a firstdetection signal and a second detection signal responsive to the inputsignal, the input circuit further operable to generate the firstdetection signal at a first activation level and the second detectionsignal at a second activation level responsive to the received inputsignal having approximately a mode-entry value; and an output circuitcoupled to the input circuit, the output circuit configured to receivethe first and second detection signals, the output circuit operable togenerate a mode-entry signal indicative of mode entry responsive to thefirst and second detection signals being at the first and secondactivation levels, respectively, for a mode-entry time.
 80. The modedetection circuit of claim 79, wherein the input circuit comprises: afirst comparison circuit having a first input adapted to receive theinput signal, a second input coupled to a first reference voltage, andan output adapted to generate the first detection signal; and a secondcomparison circuit having a first input adapted to receive the inputsignal, a second input coupled to a second reference voltage, and anoutput adapted to generate the second detection signal.
 81. The modedetection circuit of claim 80, wherein at least one of the first andsecond comparison circuits comprises a differential amplifier.
 82. Themode detection circuit of claim 79, wherein the input circuit comprises:a load element having a first and second terminals; a first switchingcircuit having a control terminal adapted to receive the input signal, afirst signal terminal coupled to a first reference voltage, and a secondsignal terminal coupled to the first terminal of the load element andadapted to generate the first detection signal; and a second switchingcircuit having a control terminal adapted to receive the input signal, afirst signal terminal coupled to a second reference voltage, and asecond signal terminal coupled to the second terminal of the loadelement and adapted to generate the second detection signal.
 83. Themode detection circuit of claim 82, wherein the load element comprises aresistor, the first switching circuit comprises a p-channelmetal-oxide-semiconductor (PMOS) transistor, the second switchingcircuit comprises an n-channel metal-oxide-semiconductor (NMOS)transistor, and wherein the mode-entry value comprises a voltage valuethat causes both the PMOS and NMOS transistors to conduct.
 84. The modedetection circuit of claim 79, wherein the output circuit comprises: athird switching circuit having a control terminal adapted to receive thesecond detection signal, a first signal terminal adapted to receive thefirst detection signal; and a second signal terminal adapted to developa charging signal; and an energy storage element coupled to the thirdswitching circuit to receive the charging signal, the energy storageelement storing energy from the charging signal to develop themode-entry signal, the developed mode-entry signal having a value thatis a function of a rate at which the storage element stores energy and aduration of time that the input signal is approximately at themode-entry value.
 85. The mode detection circuit of claim 84, whereinthe third switching circuit comprises a PMOS transistor, and wherein theenergy storage element comprises a capacitor coupled between the secondsignal terminal of the third switching circuit and a reference voltage,a resistor coupled in parallel with the capacitor, and a transistorhaving a first and second signal terminals coupled in parallel with thecapacitor and having a control terminal adapted to received a clocksignal, the transistor coupling the first and second signal terminalstogether to discharge the capacitor responsive to the clock signal. 86.The mode detection circuit of claim 85, wherein the energy storageelement further comprises a comparator having an input adapted toreceive the mode-entry signal and an output, the comparator generating amode-latch signal on the output responsive to the mode-entry signalexceeding a threshold value.
 87. The mode detection circuit of claim 84,wherein the third switching circuit comprises a PMOS transistor, andwherein the energy storage element comprises a capacitor coupled betweenthe second signal terminal of the third switching circuit and areference voltage, and a transistor having signal terminals coupled inparallel with the capacitor and having a control terminal adapted toreceived a clock signal, the transistor coupling the signal terminalstogether to discharge the capacitor responsive to the clock signal. 88.The mode detection circuit of claim 87, wherein the energy storageelement further comprises a comparator having an input adapted toreceive the mode-entry signal and an output, the comparator generating amode-latch signal on the output responsive to the mode-entry signalexceeding a threshold value.
 89. The mode detection circuit of claim 84,wherein the third switching circuit comprises a PMOS transistor, andwherein the energy storage element comprises a resistor coupled betweenthe second signal terminal of the third switching circuit and areference voltage, and a transistor having signal terminals coupled inparallel with the capacitor and having a control terminal adapted toreceived a clock signal, the transistor coupling the signal terminalstogether to short-circuit the resistor responsive to the clock signal.90. The mode detection circuit of claim 89, wherein the energy storageelement further comprises a comparator having an input adapted toreceive the mode-entry signal and an output, the comparator generating amode-latch signal on the output responsive to the mode-entry signalexceeding a threshold value.
 91. A memory device, comprising: an addressbus; a control bus; a data bus; an address decoder coupled to theaddress bus; a control circuit coupled to the control bus; a data accesscircuit coupled to the data bus; a memory-cell array coupled to theaddress decoder, control circuit, and data access circuit, thememory-cell array having a plurality of memory cells arranged in rowsand columns; and a mode detection circuit coupled to the memory-cellarray, the mode detection circuit having an input and an output, theinput adapted to receive an input signal having a first and secondvalues when in a first mode, the mode detection circuit operable togenerate on the output a mode-entry signal indicative of entering asecond mode responsive to the received input signal being approximatelyat a third value for a mode-entry time.
 92. The memory device of claim91, wherein the mode detection circuit comprises: a load element havinga first and second terminals; a first switching circuit having a controlterminal adapted to receive the input signal, a first signal terminalcoupled to a first reference voltage, and a second signal terminalcoupled to the first terminal of the load element and adapted togenerate a first detection signal; a second switching circuit having acontrol terminal adapted to receive the input signal, a first signalterminal coupled to a second reference voltage, and a second signalterminal coupled to the second terminal of the load element and adaptedto generate a second detection signal; and an output circuit adapted toreceive the first and second detection signals, the output circuitoperable to generate the mode-entry signal responsive to the inputsignal being approximately at the third value for the mode-entry time.93. The memory device of claim 92, wherein the load element comprises aresistor, the first switching circuit comprises a p-channelmetal-oxide-semiconductor (PMOS) transistor, and the second switchingcircuit comprises an n-channel metal-oxide-semiconductor (NMOS)transistor.
 94. The memory device of claim 92, wherein the outputcircuit comprises: a third switching circuit having a control terminaladapted to receive the second detection signal, a first signal terminaladapted to receive the first detection signal, and a second signalterminal adapted to develop a charging signal; and an energy storageelement adapted to receive the charging signal and store energy from thecharging signal to develop the mode-entry signal, the developedmode-entry signal having a value as a function of a rate at which theenergy storage element stores energy and a duration of time that theinput signal is approximately at the third value.
 95. The memory deviceof claim 94, wherein the output circuit further comprises a comparatorhaving an input adapted to receive the mode-entry signal and an output,the comparator operable to generate a mode-latch signal on the outputresponsive to the mode-entry signal exceeding a threshold value.
 96. Thememory device of claim 94, wherein the third switching circuit comprisesa PMOS transistor, and wherein the energy storage element comprises acapacitor coupled between the second signal terminal of the thirdswitching circuit and the second reference voltage, and a transistorhaving a first and second signal terminals coupled in parallel with thecapacitor and a control terminal adapted to received a clock signal, thetransistor coupling the first and second signal terminals together todischarge the capacitor responsive to the clock signal.
 97. The memorydevice of claim 94, wherein the third switching circuit comprises a PMOStransistor, and wherein the energy storage element comprises a resistorcoupled between the second signal terminal of the third switchingcircuit and the second reference voltage, and a transistor having afirst and second signal terminals coupled in parallel with the capacitorand a control terminal adapted to received a clock signal, thetransistor coupling the first and second signal terminals together toshort-circuit the resistor responsive to the clock signal.
 98. Thememory device of claim 91, wherein the memory device comprises a staticrandom access memory (SRAM).
 99. A computer system, comprising: a datainput device; a data output device; a data storage device; and acomputing circuitry coupled to the data input device, data outputdevice, and data storage device, the computing circuitry having a memorydevice, the memory device comprising: an address bus; a control bus; adata bus; an address decoder coupled to the address bus; a controlcircuit coupled to the control bus; a data access circuit coupled to thedata bus; a memory-cell array coupled to the address decoder, controlcircuit, and data access circuit, the memory-cell array having aplurality of memory cells arranged in rows and columns; and a modedetection circuit coupled to the memory-cell array, the mode detectioncircuit having an input and an output, the input adapted to receive aninput signal having a first and second values when in a first mode, themode detection circuit operable to generate on the output a mode-entrysignal indicative of entering a second mode responsive to the receivedinput signal being approximately at a third value for a mode-entry time.100. The computer system of claim 99, wherein the mode detection circuitcomprises: a load element having a first and second terminals; a firstswitching circuit having a control terminal adapted to receive the inputsignal, a first signal terminal coupled to a first reference voltage,and a second signal terminal coupled to the first terminal of the loadelement and adapted to generate a first detection signal; a secondswitching circuit having a control terminal adapted to receive the inputsignal, a first signal terminal coupled to a second reference voltage,and a second signal terminal coupled to the second terminal of the loadelement and adapted to generate a second detection signal; and an outputcircuit adapted to receive the first and second detection signals, theoutput circuit operable to generate the mode-entry signal responsive tothe input signal being approximately at the third value for themode-entry time.
 101. The computer system of claim 100, wherein the loadelement comprises a resistor, the first switching circuit comprises ap-channel metal-oxide-semiconductor (PMOS) transistor, and the secondswitching circuit comprises an n-channel metal-oxide-semiconductor(NMOS) transistor.
 102. The computer system of claim 100, wherein theoutput circuit comprises: a third switching circuit having a controlterminal adapted to receive the second detection signal, a first signalterminal adapted to receive the first detection signal, and a secondsignal terminal adapted to develop a charging signal; and an energystorage element adapted to receive the charging signal and store energyfrom the charging signal to develop the mode-entry signal, the developedmode-entry signal having a value as a function of a rate at which theenergy storage element stores energy and a duration of time that theinput signal is approximately at the third value.
 103. The computersystem of claim 102, wherein the output circuit further comprises acomparator having an input adapted to receive the mode-entry signal andan output, the comparator operable to generate a mode-latch signal onthe output responsive to the mode-entry signal exceeding a thresholdvalue.
 104. The computer system of claim 102, wherein the thirdswitching circuit comprises a PMOS transistor, and wherein the energystorage element comprises a capacitor coupled between the second signalterminal of the third switching circuit and the second referencevoltage, and a transistor having a first and second signal terminalscoupled in parallel with the capacitor and a control terminal adapted toreceived a clock signal, the transistor coupling the first and secondsignal terminals together to discharge the capacitor responsive to theclock signal.
 105. The computer system of claim 102, wherein the thirdswitching circuit comprises a PMOS transistor, and wherein the energystorage element comprises a resistor coupled between the second signalterminal of the third switching circuit and the second referencevoltage, and a transistor having a first and second signal terminalscoupled in parallel with the capacitor and a control terminal adapted toreceived a clock signal, the transistor coupling the first and secondsignal terminals together to short-circuit the resistor responsive tothe clock signal.
 106. The computer system of claim 99, wherein thememory device comprises a static random access memory (SRAM).